Improving the hardware complexity by exploiting the reduced dynamics-based fractional order systems

Fractional calculus is nding increased usage in the modeling and control of nonlinear systems with the enhanced robustness. However, from the implementation perspectives, the simultaneous modeling of the systems and the design of controllers with fractional-order operators can bring additional advantages. In this paper, a fractional order model of a nonlinear system along with its controller design and its implementation on a eld programmable gate array (FPGA) is undertaken as a case study. Overall, three variants of the controllers are designed, including classical sliding mode controller, fractional controller for an integer model of the plant, and a fractional controller for a fractional model of the plant (FCFP). A high-level synthesis approach is used to map all the variants of the controllers on FPGA. The integro-differential fractional operators are realized with in nite impulse response lters architecturally implemented as cascaded secondorder sections to withstand quantization effects introduced by xed-point computations necessary for FPGA implementations. The experimental results demonstrate that the fractional order sliding mode controllerbased on fractional order plant (FCFP) exhibits reduced dynamics in sense of fractional integration and differentials. It is further veri ed that the FCFP is as robust as the classical sliding mode with comparable performance and computational resources

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems

Reconfigurable systems are gaining an increasing interest in the domain of safety-critical applications, for example in the space and avionic domains. In fact, the capability of reconfiguring the system during run-time execution and the high computational power of modern Field Programmable Gate Arrays (FPGAs) make these devices suitable for intensive data processing tasks. Moreover, such systems must also guarantee the abilities of self-awareness, self-diagnosis and self-repair in order to cope with errors due to the harsh conditions typically existing in some environments. In this paper we propose a selfrepairing method for partially and dynamically reconfigurable systems applied at a fine-grain granularity level. Our method is able to detect, correct and recover errors using the run-time capabilities offered by modern SRAM-based FPGAs. Fault injection campaigns have been executed on a dynamically reconfigurable system embedding a number of benchmark circuits. Experimental results demonstrate that our method achieves full detection of single and multiple errors, while significantly improving the system availability with respect to traditional error detection and correction methods

Switch based high cardinality node detection

The detection of supernodes with high cardinality is of interest for network monitoring and security. Existing schemes for supernode detection rely on data structures that are independent of the switching functions. This means that for each packet that traverses the switch, both the switching table and the supernode detection structure have to be checked which requires significant memory bandwidth. This can create a bottleneck and reduce the speed of the switch, especially for software implementations. In this letter, a scheme that performs supernode detection as part of Ethernet switching and does not require additional memory accesses nor separated data structures is presented. The scheme has been implemented and compared with the existing methods. The results show that the proposed scheme can reliably identify supernodes while providing a speed up of more than 15% when compared with the existing solutions.This work was supported in part by the Higher Education Commission (HEC) Pakistan and the Ministry of Planning, Development and Special Initiatives under National Centre for Cyber Security; in part by the ACHILLES Project PID2019-104207RB-I00 and the Go2Edge network RED2018-102585-T funded by the Spanish Ministry of Science and Innovation; and in part by the Madrid Community Research Project TAPIR-CM under Grant P2018/TCS4496

Fault-tolerant polyphase filters-based decimators for SRAM-based FPGA implementations

To reduce the oversampling rate of baseband signals, decimation is widely used in digital communication systems. Polyphase filters (PPFs) can be used to efficiently implement decimators. SRAM-based FPGAs provide large amounts of resources combined with flexibility and are a popular option for the implementation of communication receivers. However, they are sensitive to soft errors, which limit their application in harsh environments, such as space. An initial reliability study on SRAM-based FPGA implemented decimation shows that the soft errors on around 5% of the critical bits in the configuration memory of the decimator would degrade the decimated signal dramatically. Based on this result, this paper proposes an efficient fault tolerance scheme, in which the high correlation between adjacent PPFs outputs is utilized to tolerate the fault of a single-phase filter, and a duplicate and comparison structure is used to protect the fault tolerance logic. Hardware implementation and fault injection experiments show that the proposed scheme can drastically reduce the number of critical bits that cause severe output degradation with 1.5x resource usage and 0.75x maximum frequency relative to the unprotected decimator. Therefore, the proposed scheme can be an alternative to Triple Modular Redundancy that more than triples the use of resources.This work is supported by Natural Science Funds of China (Grant No. 62171313) and is partially supported by the ACHILLES project PID2019-104207RB-I00 funded by the Spanish Ministry of Science and Innovation and by the Madrid Community research project TAPIR-CM grant no. P2018/TCS-4496

Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs

Leading zero count (LZC) is a fundamental building block in floating-point arithmetic and data sketches. These applications are increasingly being implemented on field-programmable gate arrays (FPGAs), however, existing architectures for LZC target application-specific integrated circuits and to the best of our knowledge specific LZC implementations tailored to FPGA structures have not been presented. In this letter, the implementation of LZC on Xilinx FPGA is considered and it is shown that by carefully adapting the LZC design to the FPGA structure, more efficient implementations can be obtained. In more detail, LZC designs for different bit widths are presented and evaluated. The results show that significant reductions in the FPGA resources needed are obtained that reach 33% lookup tables (LUTs) saving for 32-bit vectors and 20% LUTs saving for 64-bit vectors.The work of Pedro Reviriego was supported in part by the ACHILLES Project funded by the Spanish Ministry of Science and Innovation under Grant PID2019-104207RB-I00; and in part by the Madrid Government (Comunidad de Madrid-Spain) through the Multiannual Agreement with Universidad Carlos III de Madrid (UC3M) in the line of Excellence of University Professors under Grant EPUC3M21 in the Context of the V Plan Regional de Investigación Científica e Innovación Tecnológica (V PRICIT).Publicad

Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Reed–Solomon erasure codes (RS-ECs) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is implemented on a field-programmable gate array (FPGA) in a space platform, it will suffer single-event upsets (SEUs) that can cause failures. In this article, the reliability of an RS-EC decoder implemented on an FPGA when there are errors in the user memory is first studied. Then, a fault detection and location scheme is proposed based on partial reencoding for the faults in the user memory of the RS-EC decoder. Furthermore, check bits are added in the generator matrix to improve the fault location performance. The theoretical analysis shows that the scheme could detect most faults with small missing and false detection probability. Experimental results on a case study show that more than 90% of the faults on user memory could be tolerated by the decoder, and all the other faults can be detected by the fault detection scheme when the number of erasures is smaller than the correction capability of the code. Although false alarms exist (with probability smaller than 4%), they can be used to avoid fault accumulation. Finally, the fault location scheme could accurately locate all the faults. The theoretical estimates are very close to the experiment results, which verifies the correctness of the analysis done.This work was supported in part by the National Natural Science Foundation of China under Grant 61501321, in part by the China Postdoctoral Science Foundation and Luoyang Newvid Technology Company, Ltd., and in part by the ACHILLES Project PID2019-104207RB-I00 funded by the Spanish Ministry of Science and Innovation

VR-ZYCAP: A versatile resourse-level ICAP controller for ZYNQ SOC

This article belongs to the Special Issue Architecture and CAD for Field-Programmable Gate Arrays (FPGAs)Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.This research was funded by Spanish Ministry of Science and Innovation under the ACHILLES project, grant number PID2019-104207RB-I00 and by Taif University Researchers Supporting fund, grant number (TURSP-2020/144), Taif University, Taif, Saudi Arabia

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search. All these signal processing operations make real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) a challenge. In this paper, a novel design approach is proposed for the FPGA-implementation of the MUSIC algorithm. This approach enables a significant reduction in both FPGA resources and latency. In more detail, the proposed design enables the estimation of DoA in real-time scenarios in 2μ sec with 30% to 50% fewer resources as compared to existing techniques.The work of Pedro Reviriego was supported in part by the Architecting Intelligent Cost-effective Central Offices to enable 5G Tactile Internet (ACHILLES) through the Spanish Ministry of Economy and Competitivity under Project PID2019-104207RB-I00, in part by the Madrid Government (Comunidad de Madrid-Spain) through the Multiannual Agreement with Universidad Carlos III de Madrid (UC3M) in the line of Excellence of University Professors under Grant EPUC3M21, and in part by the Context of the V Plan Regional de Investigación Científica e Innovación Tecnológica (V PRICIT) (Regional Program of Research and Technological Innovation)

PREVALENCE OF DENGUE VIRAL INFECTION IN PESHAWAR, KPK, PAKISTAN

Background: Dengue is a widespread mosquito-borne viral infection in human beings, which is a major public health concern all over the world. In recent years, dengue is predominant in the tropics and subtropics with a high incidence and increased considerably over the last three decades. Objective: To investigate the prevalence of dengue in Peshawar, Khyber Pakhunkhwa, Province of Pakistan. A total of 823 samples were collected from 823 patients by puncturing the vein in aseptic condition. Serum of patient was analyzed by Immunochromatography technique (ICT). Results: Out of patients, 671 were male and 152 were female. Among the total of 823 samples, 196 (23.81%) patients were positive for Dengue Non-Structure 1 (NS1) while 627 (76.18%) were negative. In male patients 147 (21.90%) were positive for Dengue NS1 while 524 (78.09%) were negative. Out of 152 (18.46%) female patients 49 (32.23%) were positive for Dengue NS1 and remaining 103 (67.76%) were negative. Conclusion: It is concluded that the prevalence of dengue infection is higher in male than in female due to susceptibility of male to certain risk of dengue. Key Words: Prevalence, Dengue viral infection, Peshawa